Linux* Processor Microcode Data File

Version: 20180807 (Previously Released) Date: 8/7/2018

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Detailed Description

Intel Processor Microcode Package for Linux*

CPU microcode is a mechanism to correct certain errata in existing systems.
The normal preferred method to apply microcode updates is using the system
BIOS, but for a subset of Intel's processors this can be done at runtime
using the operating system. This package contains those processors that
support OS loading of microcode updates.

The target user for this package are OS vendors such as Linux* distributions
for inclusion in their OS releases. Intel recommends getting the microcode
using the OS vendor update mechanism. Expert users can of course update their
microcode directly outside the OS vendor mechanism. This method is complex and
thus could be error prone.

Microcode is best loaded from the BIOS. Certain microcode must only be applied
from the BIOS. Such processor microcode updates are never packaged in this
package since they are not appropriate for OS distribution. An OEM may receive
microcode packages that might be a superset of what is contained in this

OS vendors may choose to also update microcode that kernel can consume for early
loading. For e.g. Linux can update processor microcode very early in the kernel
boot sequence. In situations when the BIOS update isn't available, early loading
is the next best alternative to updating processor microcode. Microcode states
are reset on a power reset, hence its required to be updated everytime during
boot process.

Loading microcode using the initrd method is recommended so that the microcode
is loaded at the earliest time for best coverage. Systems that cannot tolerate
downtime may use the late reload method to update a running system without a

== About Processor Signature, Family, Model, Stepping and Platform ID ==
Processor signature is a number identifying the model and version of a
Intel processor. It can be obtained using the CPUID instruction, and can
also be obtained via the command lscpu or from the content of /proc/cpuinfo.
It's usually presented as 3 fields: Family, Model and Stepping
(In the table of updates below, they are shorten as F, MO and S).

The width of Family/Model/Stepping is 12/8/4bit, but when arranged in the
32bit processor signature raw data is like 0FFM0FMS, hexadecimal.
e.g. if a processor signature is 0x000906eb, it means
Family=0x006, Model=0x9e and Stepping=0xb

A processor product can be implemented for multiple types of platforms,
So in MSR(17H), Intel processors have a 3bit Platform ID field,
that can specify a platform type from at most 8 types.
A microcode file for a specified processor model can support multiple
platforms, so the Platform ID of a microcode (shorten as PI in the table)
is a 8bit mask, each set bit indicates a platform type that it supports.
One can find the platform ID on Linux using rdmsr from msr-tools.

== Microcode update instructions ==
-- intel-ucode/ --
intel-ucode directory contains binary microcode files named in
family-model-stepping pattern. The file is supported in most modern Linux
distributions. It's generally located in the /lib/firmware directory,
and can be updated through the microcode reload interface.

To update early loading initrd, consult your distribution on how to package
microcode files for early loading. Some distros use update-initramfs or dracut.
As recommended above, please use the OS vendors are recommended method to ensure
microcode file is updated for early loading before attempting the late-load
procedure below.

To update the intel-ucode package to the system, one need:
1. Ensure the existence of /sys/devices/system/cpu/microcode/reload
2. Copy intel-ucode directory to /lib/firmware, overwrite the files in
3. Write the reload interface to 1 to reload the microcode files, e.g.
  echo 1 > /sys/devices/system/cpu/microcode/reload

If you are using the OS vendor method to update microcode, the above steps may
have been done automatically during the update process.

-- intel-ucode-with-caveats/ --
This directory holds microcode that might need special handling.
BDX-ML microcode is provided in directory, because it need special commits in
the Linux kernel, otherwise, updating it might result in unexpected system
OS vendors must ensure that the late loader patches (provided in
linux-kernel-patches\) are included in the distribution before packaging the
BDX-ML microcode for late-loading.

== 20180807 Release ==
-- Updates upon 20180703 release --
Processor             Identifier     Version       Products
Model        Stepping F-MO-S/PI      Old->New
---- new platforms ----------------------------------------
WSM-EP/WS    U1       6-2c-2/03           0000001f Xeon E/L/X56xx, W36xx
NHM-EX       D0       6-2e-6/04           0000000d Xeon E/L/X65xx/75xx
BXT          C0       6-5c-2/01           00000014 Atom T5500/5700
APL          E0       6-5c-a/03           0000000c Atom x5-E39xx
DVN          B0       6-5f-1/01           00000024 Atom C3xxx
---- updated platforms ------------------------------------
NHM-EP/WS    D0       6-1a-5/03 00000019->0000001d Xeon E/L/X/W55xx
NHM          B1       6-1e-5/13 00000007->0000000a Core i7-8xx, i5-7xx; Xeon L3426, X24xx
WSM          B1       6-25-2/12 0000000e->00000011 Core i7-6xx, i5-6xx/4xxM, i3-5xx/3xxM, Pentium G69xx, Celeon P45xx; Xeon L3406
WSM          K0       6-25-5/92 00000004->00000007 Core i7-6xx, i5-6xx/5xx/4xx, i3-5xx/3xx, Pentium G69xx/P6xxx/U5xxx, Celeron P4xxx/U3xxx
SNB          D2       6-2a-7/12 0000002d->0000002e Core Gen2; Xeon E3
WSM-EX       A2       6-2f-2/05 00000037->0000003b Xeon E7
IVB          E2       6-3a-9/12 0000001f->00000020 Core Gen3 Mobile
HSW-H/S/E3   Cx/Dx    6-3c-3/32 00000024->00000025 Core Gen4 Desktop; Xeon E3 v3
BDW-U/Y      E/F      6-3d-4/c0 0000002a->0000002b Core Gen5 Mobile
HSW-ULT      Cx/Dx    6-45-1/72 00000023->00000024 Core Gen4 Mobile and derived Pentium/Celeron
HSW-H        Cx       6-46-1/32 00000019->0000001a Core Extreme i7-5xxxX
BDW-H/E3     E/G      6-47-1/22 0000001d->0000001e Core i5-5xxxR/C, i7-5xxxHQ/EQ; Xeon E3 v4
SKL-U/Y      D0       6-4e-3/c0 000000c2->000000c6 Core Gen6 Mobile
BDX-DE       V1       6-56-2/10 00000015->00000017 Xeon D-1520/40
BDX-DE       V2/3     6-56-3/10 07000012->07000013 Xeon D-1518/19/21/27/28/31/33/37/41/48, Pentium D1507/08/09/17/19
BDX-DE       Y0       6-56-4/10 0f000011->0f000012 Xeon D-1557/59/67/71/77/81/87
APL          D0       6-5c-9/03 0000002c->00000032 Pentium N/J4xxx, Celeron N/J3xxx, Atom x5/7-E39xx
SKL-H/S/E3   R0       6-5e-3/36 000000c2->000000c6 Core Gen6; Xeon E3 v5
GLK          B0       6-7a-1/01 00000022->00000028 Pentium Silver N/J5xxx, Celeron N/J4xxx
KBL-U/Y      H0       6-8e-9/c0 00000084->0000008e Core Gen7 Mobile
CFL-U43e     D0       6-8e-a/c0 00000084->00000096 Core Gen8 Mobile
KBL-H/S/E3   B0       6-9e-9/2a 00000084->0000008e Core Gen7; Xeon E3 v6
CFL-H/S/E3   U0       6-9e-a/22 00000084->00000096 Core Gen8
CFL-H/S/E3   B0       6-9e-b/02 00000084->0000008e Core Gen8 Desktop

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